Passivation Cracking Analyses of Micro-structures of IC Packages

The passivation cracking of Micro-structures of IC packages is studied by maximum principal stress theory using a certain 2D FEM model with different design parameters, pitch of lines, width of line, thickness of epoxy, thickness of dielectric layer, thickness of glue, the glue material’s yielding stress and Aluminium yielding stress (following as “d”, “w”, “t_epo”, “t_Teos”, “t_glue” “sy_glue” and “sy_al” respectively). For different critical process steps, the final process temperature is acted as a representative parameter to analyze its impact. Furthermore, Response Surface Model (RSM) of principal stress is established using any two design parameters. Results show that “d”, “w”, “t_epo”, “sy_glue” and “sy_al” will have great influence on passivation cracking while “t_Teos” have a little impact. Introduction Reliability of the Integrated Circuits (ICs) is one of the major concerns for semiconductor industry. Thermo-mechanical failures, such as passivation cracks, pattern shift, loose bond balls, wire break, voids, buckling, hillocks, delamination and(or) debonding, are often observed during manufacturing processes, qualification tests and field applications [1,2] . To predict the phenomena of passivation cracking, the analyses of stress distribution in dielectric layers are carried out here. The stresses are obtained by means of Finite Element Method. And a two-dimensional model is employed to represent a cross-section of the IC to find this influence by varying the dimensional parameters and to quantify the stress occurrence during each step of the whole manufacturing process. The principal stress method is used here, which calculates the stress distribution and applies the maximum principal stresses as the failure criteria. From these analyses, we can find the dangerous designed structure schedules and draw out some useful design rules for next generational products. Finite Element Models Typical FE Meshes. We use two-dimensional plane strain FE models to perform the simulations. The evaluated geometry is visualized in Fig.2, which shows a local part of the interconnect structure on the die in the IC package. In this model, there are 6 layers on the silicon substrate consisting of metal and dielectric materials in the interconnect structure and a compound layer on top. Due to the large range in dimensions the mesh density (50nmx50nm) is much larger in the interconnect layers than in the silicon and compound layers. The typical FE meshes of dielectric layer and metal line are shown in Fig.3 (shown area: 5190nmx2625nm). Here the TiN is applied to be instead of Ti material in computations for simplification. Key Engineering Materials Vols. 324-325 (2006) pp 515-518 online at http://www.scientific.net © (2006) Trans Tech Publications, Switzerland Online available since 2006/Nov/15 All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of the publisher: Trans Tech Publications Ltd, Switzerland, www.ttp.net. (ID: 130.203.133.33-14/04/08,11:28:00) Fig.1 Typical evaluated FEM geometry Fig.2 Typical FE mesh of dielectric layer Geometry. In these calculations, model parameters are categorized into constant and varying parameters, as shown in Table1. Table1 Geometrical parameters of the 2D models material symbol value or varying range(mm) Fixed parameters lower boundary upper boundary Silicon thickness Si t_Si 0.38 Al layer thickness Al(Cu) t_Al 0.88e-3 Ti layer thickness Ti t_Ti 7.50e-6 TiN layer thickness TiN t_TiN 30e-6 Analysed package length L 15